CSC364 Computer Architecture, Smith College
Homework Assignment 3, due February 20th, 2002
1) Problem A.14 Page 708.
There is a mistake in the problem statement. It should say that "Thus, the sum output is valid after 30ns and the carry output after 20ns." The book says 0ns for the carry, and that is incorrect. The sum has 3 levels of gates (inverters, ANDs and OR) and the carry has 2 levels (AND and OR).
2) Design a (clocked) D flip-flip that uses only NAND gates.
3) Devise a circuit that would take in 2 inputs and produce 2 outputs.
The inputs are R and S of an S-R flip-flop. The outputs are R and S
unless R and S are both 1 and in that case the outputs will both be 0.