CSC400-Circuit Design on FPGA chips using VHDL

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CircuitVHDL.pngXLinxCoolRunnerCPLD.jpg

Indpendent Study. Fall 2011. Tiffany Liu

  • D. Thiebaut, I.S. adviser



  • Description:

  FPGA stands for Field-Programmable Gate Array and is a design independent integrated circuit. A FPGA has programmable logic blocks, which are analogous to logic gate chips, decoder chips, multiplexer chips, etc., and programmable switching matrices, which are analogous to the wires used to connect the different aforementioned chips. The advantage of having an integrated circuit that is field-programmable is that it allows users to design more complicated circuit systems in a more time and cost efficient manner since all the "re-wiring" is done via software programming--there is no need to re-route physical wires.

  VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language, which is used to write code for circuit synthesis and simulation. It is important to note that VHDL is a standardized language and is technology and vendor independent, which makes it portable across platforms and reusable. Two immediate applications of VHDL are in ASICs (Application Specific Integrated Circuits) and Programmable Logic Devices, such as the FPGA that will be used for this independent study.

  The purpose of this independent study is to investigate and learn how FPGAs work and how to control the FPGA using VHDL. The ultimate goal of this project would be to redesign the labs used in CSC 270 such that the students can use FPGAs and VHDL to create circuit systems such as three bit adders and majority voters instead of using physical wires and chips.

  It is important to note that the hardware that is being used for this independent study is a CPLD (Complex Programmable Logic Device), which can be considered a hybrid of sorts between a PAL (Programmable Array Logic) and a FPGA. Both PALs and CPLDs have non-volatile memory, which means that they run when powered, whereas FPGAs have RAM-based memory, which means that they need to be programmed before they can run every time they get rebooted. The number of logic blocks in a PAL is usually on the order of hundreds and in a FPGA is usually on the order of tens of thousands to millions. The number of logic blocks in a CPLD is somewhere in between the two--on the order of thousands to tens of thousands. The difference in the number of logic blocks of a FPGA and that of a CPLD makes the FPGA more flexible, but far more complicated to design in comparison to the CPLD. Another key architectural difference between a FPGA and a CPLD is that the FPGA is internally based on Look-up Tables (LUT), which allows the FPGA to have built-in, higher-level logic functions such as adders, multipliers, decoders, etc., whereas the CPLD forms logic functions with sea of gates (sums of products).


  • Resources:
    • FPGA Wikipedia
    • CPLD Wikipedia
    • HDL Chip Design: A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog, Douglas J. Smith, Doone Publications, Jun. 1996.
    • Verilog HDL: A Guide to Digital Design and Synthesis, Samir Palnitkar, SunSoft Press, 1996.