CSC270 Labs -- CSC400-Circuit Design F2011

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CSC270 Lab 2

  • Author: Tiffany Liu
  • Date Created: November 12, 2011

2-Bit Adder

  • A 2-bit adder has the following truth table:
a  b  |  c  s
------|-------
0  0  |  0  0
0  1  |  0  1       c = carry, s = sum
1  0  |  0  1
1  1  |  1  0
  • From this truth table, we can get the logical equation for c and s as follows:
c = a . b

s = a' . b + a . b' = a ^ b

Schematics

  1. Open ISE Design Suite: Start > Programs > Xilinx ISE Design Suite 11 > Project Navigator.
  2. Create a new project by selecting the New Project option from the Getting Started menu or by selecting Select File > New Project. This brings up a Dialog box where you can enter the desired project name and location. Choose a meaningful name. You can also place optional comments for your project in the Description text box. Choose Schematic for the Top-level source type.
  3. After clicking Next, select the proper Family, Device, Package, Speed, and Preferred Language for your project. For our CPLD, choose CoolRunner2 CPLDs for Family, XC2C256 for Device, TQ144 for Package, -7 for Speed, and Verilog for Preferred Language. Make sure the Enable Enhanced Design Summary box is checked.
  4. The next two dialog boxes give the option of adding new or existing source files to the project. We will fulfill these steps later, so click Next.
  5. Finally, you should see the Project Summary. Make sure all settings are correct before clicking Finish (any modifications to the settings can be made by clicking the Back button.
  6. Once the new project has been created, two sources are listed in the Design panel - the project file name and the targeted device.
  7. Add a new source file. To do this, either right-click on the target device in the Design panel and choose New Source or go to Project > New Source.
  8. Select Schematic for the Source Type, give the file a meaningful name, and click Next and then Finish.
  9. Once the new Schematic file has been created, it should appear in the Sources panel. Double click on the file to open it in the Schematic Capture Window.
  10. The following figure contains descriptions for the tools necessary for creating a basic digital circuit using Schematic Capture:

SchematicCaptureScreen.png

Courtesy of Annotated Xilinx ISE WebPACK Schematics Tutorial


  1. Double click on the new Schematic source that was just created. Under the Symbols tab, choose Logic for the Category. Using the available logic gates from the list, wire up a circuit following the logic equations for c and s from above. NOTE: Remember that everything is active low on the CoolRunner-II, so be sure to invert the inputs and the outputs to have the CPLD behave in the way that is described by the truth table. Add markers to indicate a, b, carry, and sum. To change the name of markers that are added, double-click on the marker. This brings up the Object Properties dialog box. Highlight Nets and change the Name attribute. The following is an example Schematic:

TwoBitAdderSchematic.png

  1. Add another new source to the project.
  2. Choose Implementations Constraint File as the type.
  3. To edit the .ucf file, select it in the Sources window, expand the User Constraints option in the Processes window below and double-click Edit Constraints (Text). A blank text editor should appear.
  4. Declare a net titled A and assign it to Pin 124. Declare a net titled B and assign it to Pin 38. These are the two switches sw1 and sw0 on the CoolRunner-II.
  5. Declare another net and title it Carry and assign it to Pin 68, and a final net and title it Sum and assign it to Pin 69. These are two LEDs (LED1 and LED0) on the CoolRunner-II.
NET A        LOC = P124;
NET B        LOC = P38;

NET Carry    LOC = P68;
NET Sum      LOC = P69;
  1. Generate programming file: Go to the Processes window and double-click on Generate Programming File. Debug any errors that may occur. Once the program generation processes comes to a completion, you can upload the file to your CoolRunner-II.
  2. Open the CoolRunner-II Utility Window. Click the Erase button to erase pre-loaded programming file from your CoolRunner-II.
  3. Next, click on "..." and navigate to your project folder to find the .jed file. Double-click on the .jed file and click on Program to load it into your CoolRunner-II.
  4. Double check that your CPLD is functioning properly.

TwoBitAdder.jpg

Verilog

  1. Open ISE Design Suite: Start > Programs > Xilinx ISE Design Suite 11 > Project Navigator.
  2. Create a new project by selecting the New Project option from the Getting Started menu or by selecting Select File > New Project. This brings up a Dialog box where you can enter the desired project name and location. Choose a meaningful name. You can also place optional comments for your project in the Description text box. Choose HDL for the Top-level source type.
  3. After clicking Next, select the proper Family, Device, Package, Speed, and Preferred Language for your project. For our CPLD, choose CoolRunner2 CPLDs for Family, XC2C256 for Device, TQ144 for Package, -7 for Speed, and Verilog for Preferred Language. Make sure the Enable Enhanced Design Summary box is checked.
  4. The next two dialog boxes give the option of adding new or existing source files to the project. We will fulfill these steps later, so click Next.
  5. Finally, you should see the Project Summary. Make sure all settings are correct before clicking Finish (any modifications to the settings can be made by clicking the Back button.
  6. Once the new project has been created, two sources are listed in the Design panel - the project file name and the targeted device.
  7. Add a new source file. To do this, either right-click on the target device in the Design panel and choose New Source or go to Project > New Source.
  8. Select Verilog Module for the Source Type, give the file a meaningful name, and click Next.
  9. You should now have the option of defining top-level ports for the new Verilog module. Type in A and B for input ports and Carry and Sum for output ports. Click Next.
  10. Once the new Verilog file has been created, the HDL Editor Window displays the source code.
  11. The following is the code used for the two-bit adder:
//Reference time unit set to 1 nanosecond and precision is 1 picosecond
 `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:             Smith College
// Engineer:            Tiffany Q. Liu
// 
// Create Date:    	22:19:35 10/29/2011 
// Module Name:    	TwoBitAdder.v 
// Project Name:	TwoBitAdder-Verilog 
// Target Devices:	CoolRunner-II  
// Description:         Verilog description of a 2-Bit Adder.
//
//
// Revision: 		11/08/11
// Revision 1.01 - File Created 
//
//////////////////////////////////////////////////////////////////////////////////
module TwoBitAdder(
	input A,
	input B,
	output Carry,
	output Sum
   );

//Internal wire declaration
wire iA, iB;	                        //Inverse of A and B
wire iCarry, iSum;			//Inverse of Carry and Sum

//Gate Instantiations:

//Create inverse A and B signals:
not (iA, A);
not (iB, B);

//Create inverse Carry and Sum signals:
and (iCarry, iA, iB);
xor (iSum, iA, iB);

//Create Carry and Sum signals:
not (Carry, iCarry);
not (Sum, iSum);

endmodule
 
  1. Add another new source to the project.
  2. Choose Implementations Constraint File as the type.
  3. To edit the .ucf file, select it in the Sources window, expand the User Constraints option in the Processes window below and double-click Edit Constraints (Text). A blank text editor should appear.
  4. Declare a net titled A and assign it to Pin 124. Declare a net titled B and assign it to Pin 38. These are the two switches sw1 and sw0 on the CoolRunner-II.
  5. Declare another net and title it Carry and assign it to Pin 68, and a final net and title it Sum and assign it to Pin 69. These are two LEDs (LED1 and LED0) on the CoolRunner-II.
NET A        LOC = P124;
NET B        LOC = P38;

NET Carry    LOC = P68;
NET Sum      LOC = P69;
  1. Generate programming file: Go to the Processes window and double-click on Generate Programming File. Debug any errors that may occur. Once the program generation processes comes to a completion, you can upload the file to your CoolRunner-II.
  2. Open the CoolRunner-II Utility Window. Click the Erase button to erase pre-loaded programming file from your CoolRunner-II.
  3. Next, click on "..." and navigate to your project folder to find the .jed file. Double-click on the .jed file and click on Program to load it into your CoolRunner-II.
  4. Double check that your CPLD is functioning properly.

TwoBitAdder.jpg

ISE Simulator

  1. Re-open the Verilog file for the 2-Bit adder it was closed.
  2. Before coding the simulator module, we need to edit the Verilog module for the two bit adder to remove the inverter gates from the inputs and outputs:
//Reference time unit set to 1 nanosecond and precision is 1 picosecond
 `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:             Smith College
// Engineer:            Tiffany Q. Liu
// 
// Create Date:    	22:19:35 10/29/2011 
// Module Name:    	TwoBitAdder.v
// Project Name:	TwoBitAdder-Verilog 
// Target Devices:	CoolRunner-II  
// Description:         Verilog description of a 2-Bit Adder.
//
//
// Revision: 		11/08/11
// Revision 1.01 - File Created 
//
//////////////////////////////////////////////////////////////////////////////////
module TwoBitAdder(
	input A,
	input B,
	output Carry,
	output Sum
   );

//Gate Instantiations:

//Create Carry and Sum signals:
and (Carry, A, B);
xor (Sum, A, B);

endmodule
 
  1. After editing the Verilog module, add a new source to the project. To do this, either right-click on the target device in the Design panel and choose New Source or go to Project > New Source. Choose Verilog Test Fixture for the type and give the file a meaningful name, and click Next.
  2. In the following dialog box, select the Verilog module that you just modified as the source file you want to associate with the given test fixture file. This selects the source file you actually run the simulation on. Click Next and Finish.
  3. To view and edit the Verilog test fixture, first change the selected option in the Sources for: drop-down menu from Implementation to Behavioral Simulation. Once selected, the sources panel changes slightly so that the test fixture file is the first source file under the device. The options under the Processes panel change so that the only option is the ISim Simulator.
  4. Open the Verilog test fixture in the HDL editor by double-clicking it in the Sources window. The following is the code we will use to test our Verilog two-bit adder file:
//Reference time unit set to 1 nanosecond and precision is 1 picosecond
`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:             Smith College
// Engineer:            Tiffany Q. Liu
//
// Create Date:    	02:01:00 11/09/2011 
// Module Name:    	TwoBitAdderTest.v
// Project Name:	TwoBitAdder-Verilog 
// Target Devices:	CoolRunner-II  
// Description:         Verilog Test Fixture created by ISE for module: TwoBitAdder
////////////////////////////////////////////////////////////////////////////////

module TwoBitAdderTest;

	// Inputs
	reg A;
	reg B;

	// Outputs
	wire Carry;
	wire Sum;

	// Instantiate the Unit Under Test (UUT)
	TwoBitAdder uut (
		.A(A), 
		.B(B), 
		.Carry(Carry), 
		.Sum(Sum)
	);

	initial begin

                // Initialize inputs:
		A = 0;
		B = 0;
		
                // Wait 100 ns for global reset to finish:
		#100;
			 
		#10 B = 1;
			 
		#10 A = 1;
		    B = 0;
			 
		#10 B = 1;
		
	end
      
endmodule
 
  1. Save the test fixture and select it in the sources window by clicking on it once.
  2. Go to the Processes window, expand the ISim Simulator and double-click Behavioral Check Syntax. If any errors occur, debug the code.
  3. Once behavioral syntax check has passed, double-click on Simulate Behavioral Model. The Simulate Behavioral Model process causes the ISim window to appear. Below is a guide to the ISim window with key features highlighted:

ISimScreen.png

Courtesy of Xilinx ISE Simulator (ISim) with Verilog Fixture Tutorial

  1. Use the Zoom to Full View tool, located to the right of the magnifying glasses on the simulation panel toolbar, to see the full view of the simulation.
  2. Now use the magnifying glass with the plus sign to zoom in until all relevant signals are captured in full size in the screen.
  3. Check the signals and see if they match the expected characteristics of a two-bit adder.

TwoBitAdderSignal.png

3-Bit Adder

  • A 3-bit adder has the following truth table:
a  b  d  |  c  s
---------|-------
0  0  0  |  0  0
0  0  1  |  0  1
0  1  0  |  0  1
0  1  1  |  1  0
1  0  0  |  0  1     c = carry, s = sum
1  0  1  |  1  0
1  1  0  |  1  0
1  1  1  |  1  1
  • From this truth table, we can get the logical equation for c and s as follows:
c = a' . b . d + a . b' . d + a . b. d' + a . b . d 
  = (a' + a) . (b . d) + a . (b' . d + b . d')
  = (b . d) + a . (b ^ d)

s = a' . b' . d + a' . b . d' + a . b' . d' + a . b . d
  = a' . (b' . d + b . d') + a . (b' . d' + b . d)
  = a' . (b ^ d) + a . (b ^ d)'
  = a ^ (b ^ d)

Schematics

  1. Open ISE Design Suite: Start > Programs > Xilinx ISE Design Suite 11 > Project Navigator.
  2. Create a new project by selecting the New Project option from the Getting Started menu or by selecting Select File > New Project. This brings up a Dialog box where you can enter the desired project name and location. Choose a meaningful name. You can also place optional comments for your project in the Description text box. Choose Schematic for the Top-level source type.
  3. After clicking Next, select the proper Family, Device, Package, Speed, and Preferred Language for your project. For our CPLD, choose CoolRunner2 CPLDs for Family, XC2C256 for Device, TQ144 for Package, -7 for Speed, and Verilog for Preferred Language. Make sure the Enable Enhanced Design Summary box is checked.
  4. The next two dialog boxes give the option of adding new or existing source files to the project. We will fulfill these steps later, so click Next.
  5. Finally, you should see the Project Summary. Make sure all settings are correct before clicking Finish (any modifications to the settings can be made by clicking the Back button.
  6. Once the new project has been created, two sources are listed in the Design panel - the project file name and the targeted device.
  7. Add a new source file. To do this, either right-click on the target device in the Design panel and choose New Source or go to Project > New Source.
  8. Select Schematic for the Source Type, give the file a meaningful name, and click Next and then Finish.
  9. Once the new Schematic file has been created, it should appear in the Sources panel. Double click on the file to open it in the Schematic Capture Window.
  10. The following figure contains descriptions for the tools necessary for creating a basic digital circuit using Schematic Capture:

SchematicCaptureScreen.png

Courtesy of Annotated Xilinx ISE WebPACK Schematics Tutorial


  1. Double click on the new Schematic source that was just created. Under the Symbols tab, choose Logic for the Category. Using the available logic gates from the list, wire up a circuit following the logic equations for c and s from above. NOTE: Remember that everything is active low on the CoolRunner-II, so be sure to invert the inputs and the outputs to have the CPLD behave in the way that is described by the truth table. Add markers to indicate a, b, d, carry, and sum. To change the name of markers that are added, double-click on the marker. This brings up the Object Properties dialog box. Highlight Nets and change the Name attribute. The following is an example Schematic:

ThreeBitAdderSchematic.png

  1. Add another new source to the project.
  2. Choose Implementations Constraint File as the type.
  3. To edit the .ucf file, select it in the Sources window, expand the User Constraints option in the Processes window below and double-click Edit Constraints (Text). A blank text editor should appear.
  4. Declare a net titled A and assign it to Pin 124. Declare a net titled B and assign it to Pin 38. These are the two switches sw1 and sw0 on the CoolRunner-II.
  5. Declare a net titled D and assign it to Pin 94. This is a push button btn1.
  6. Declare another net and title it Carry and assign it to Pin 68, and a final net and title it Sum and assign it to Pin 69. These are two LEDs (LED1 and LED0) on the CoolRunner-II.
NET A        LOC = P124;
NET B        LOC = P38;
NET D        LOC = P94;

NET Carry    LOC = P68;
NET Sum      LOC = P69;
  1. Generate programming file: Go to the Processes window and double-click on Generate Programming File. Debug any errors that may occur. Once the program generation processes comes to a completion, you can upload the file to your CoolRunner-II.
  2. Open the CoolRunner-II Utility Window. Click the Erase button to erase pre-loaded programming file from your CoolRunner-II.
  3. Next, click on "..." and navigate to your project folder to find the .jed file. Double-click on the .jed file and click on Program to load it into your CoolRunner-II.
  4. Double check that your CPLD is functioning properly.

ThreeBitAdderPic.jpg

Verilog

  1. Open ISE Design Suite: Start > Programs > Xilinx ISE Design Suite 11 > Project Navigator.
  2. Create a new project by selecting the New Project option from the Getting Started menu or by selecting Select File > New Project. This brings up a Dialog box where you can enter the desired project name and location. Choose a meaningful name. You can also place optional comments for your project in the Description text box. Choose HDL for the Top-level source type.
  3. After clicking Next, select the proper Family, Device, Package, Speed, and Preferred Language for your project. For our CPLD, choose CoolRunner2 CPLDs for Family, XC2C256 for Device, TQ144 for Package, -7 for Speed, and Verilog for Preferred Language. Make sure the Enable Enhanced Design Summary box is checked.
  4. The next two dialog boxes give the option of adding new or existing source files to the project. We will fulfill these steps later, so click Next.
  5. Finally, you should see the Project Summary. Make sure all settings are correct before clicking Finish (any modifications to the settings can be made by clicking the Back button.
  6. Once the new project has been created, two sources are listed in the Design panel - the project file name and the targeted device.
  7. Add a new source file. To do this, either right-click on the target device in the Design panel and choose New Source or go to Project > New Source.
  8. Select Verilog Module for the Source Type, give the file a meaningful name, and click Next.
  9. You should now have the option of defining top-level ports for the new Verilog module. Type in A, B, and D for input ports and Carry and Sum for output ports. Click Next.
  10. Once the new Verilog file has been created, the HDL Editor Window displays the source code.
  11. The following is the code used for the three-bit adder:
//Reference time unit set to 1 nanosecond and precision is 1 picosecond
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 		Smith College
// Engineer: 		Tiffany Q. Liu
// 
// Create Date:    	23:22:44 10/29/2011 
// Module Name:    	ThreeBitAdder.v 
// Project Name:	ThreeBitAdder-Verilog 
// Target Devices: 	CoolRunner-II
// Description:         Verilog description of a 3-Bit Adder
//
// Revision: 		11/08/11
// Revision 1.01 - File Created 
//
//////////////////////////////////////////////////////////////////////////////////
module ThreeBitAdder(
    input A,
    input B,
    input D,
    output Carry,
    output Sum
    );

//Internal wire declarations:
wire iA, iB, iD;	//Inverse of A, B, and D signals
wire c2, c1, c0;
wire s0;
wire iCarry, iSum;	//Inverse of Carry and Sum signals

//Gate instantiations:

//Create inverse A, B, and D signals:
not (iA, A);
not (iB, B);
not (iD, D);

//Create inverse Carry signal:
or (c0, iB, iD);
and (c1, iA, c0);
and (c2, iB, iD);
or (iCarry, c1, c2);

//Create inverse Sum signal:
xor (s0, iB, iD);
xor (iSum, iA, s0);

//Create Carry and Sum signals:
not (Carry, iCarry);
not (Sum, iSum);

endmodule

  1. Generate programming file: Go to the Processes window and double-click on Generate Programming File. Debug any errors that may occur. Once the program generation processes comes to a completion, you can upload the file to your CoolRunner-II.
  2. Open the CoolRunner-II Utility Window. Click the Erase button to erase pre-loaded programming file from your CoolRunner-II.
  3. Next, click on "..." and navigate to your project folder to find the .jed file. Double-click on the .jed file and click on Program to load it into your CoolRunner-II.
  4. Double check that your CPLD is functioning properly.

ThreeBitAdderPic.jpg

ISE Simulator

  1. Re-open the Verilog file for the 3-Bit adder if it was closed.
  2. Before coding the simulator module, we need to edit the Verilog module for the three bit adder to remove the inverter gates from the inputs and outputs:
//Reference time unit set to 1 nanosecond and precision is 1 picosecond
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 		Smith College
// Engineer: 		Tiffany Q. Liu
// 
// Create Date:    	23:22:44 10/29/2011 
// Module Name:    	ThreeBitAdder.v 
// Project Name:	ThreeBitAdder-Verilog 
// Target Devices: 	CoolRunner-II
// Description:         Verilog description of a 3-Bit Adder
//
// Revision: 		11/08/11
// Revision 1.01 - File Created 
//
//////////////////////////////////////////////////////////////////////////////////
module ThreeBitAdder(
    input A,
    input B,
    input D,
    output Carry,
    output Sum
    );

//Internal wire declarations:
wire c2, c1, c0;
wire s0;

//Gate instantiations:

//Create Carry signal:
or (c0, B, D);
and (c1, A, c0);
and (c2, B, D);
or (Carry, c1, c2);

//Create Sum signal:
xor (s0, B, D);
xor (Sum, A, s0);

endmodule
 
  1. After editing the Verilog module, add a new source to the project. To do this, either right-click on the target device in the Design panel and choose New Source or go to Project > New Source. Choose Verilog Test Fixture for the type and give the file a meaningful name, and click Next.
  2. In the following dialog box, select the Verilog module that you just modified as the source file you want to associate with the given test fixture file. This selects the source file you actually run the simulation on. Click Next and Finish.
  3. To view and edit the Verilog test fixture, first change the selected option in the Sources for: drop-down menu from Implementation to Behavioral Simulation. Once selected, the sources panel changes slightly so that the test fixture file is the first source file under the device. The options under the Processes panel change so that the only option is the ISim Simulator.
  4. Open the Verilog test fixture in the HDL editor by double-clicking it in the Sources window. The following is the code we will use to test our Verilog three-bit adder file:
//Reference time unit set to 1 nanosecond and precision is 1 picosecond
`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College
// Engineer:		Tiffany Q. Liu
//
// Create Date:         01:49:18 11/13/2011
// Design Name:         ThreeBitAdder
// Module Name:         ThreeBitAdder_Test.v
// Project Name:        ThreeBitAdder-Verilog
// Target Device:       CoolRunner-II  
// Description:         Verilog Test Fixture created by ISE for module: ThreeBitAdder
////////////////////////////////////////////////////////////////////////////////

module ThreeBitAdder_Test;

	// Inputs
	reg A;
	reg B;
	reg D;

	// Outputs
	wire Carry;
	wire Sum;

	// Instantiate the Unit Under Test (UUT)
	ThreeBitAdder uut (
		.A(A), 
		.B(B), 
		.D(D), 
		.Carry(Carry), 
		.Sum(Sum)
	);

	initial begin
		// Initialize Inputs
		A = 0;
		B = 0;
		D = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		#10 D = 1;
		
		#10 B = 1;
		    D = 0;
		
		#10 D = 1;
		
		#10 A = 1;
		    B = 0;
		    D = 0;
		
		#10 D = 1;
		
		#10 B = 1;
		    D = 0;
		
		#10 D = 1;

	end
      
endmodule
 
  1. Save the test fixture and select it in the sources window by clicking on it once.
  2. Go to the Processes window, expand the ISim Simulator and double-click Behavioral Check Syntax. If any errors occur, debug the code.
  3. Once behavioral syntax check has passed, double-click on Simulate Behavioral Model. The Simulate Behavioral Model process causes the ISim window to appear. Below is a guide to the ISim window with key features highlighted:

ISimScreen.png


Courtesy of Xilinx ISE Simulator (ISim) with Verilog Fixture Tutorial


  1. Use the Zoom to Full View tool, located to the right of the magnifying glasses on the simulation panel toolbar, to see the full view of the simulation.
  2. Now use the magnifying glass with the plus sign to zoom in until all relevant signals are captured in full size in the screen.
  3. Check the signals and see if they match the expected characteristics of a three-bit adder.

ThreeBitAdderSignal.png


CSC 270 Lab 3

  • Author: Tiffany Liu
  • Date Created: November 14, 2011

Seven Segment Display

  • The CoolRunner-II Seven Segment Display has active low anodes and cathodes.

Cool Runner II User IO Pins Reference.jpg

    • To choose a particular seven segment digit from the four to use, you need to send a low signal to one of Pins 130, 129, 128, and 126.
    • To choose a particular segment or decimal point to activate, you need to send low signals to Pins 56, 53, 60, 58, 57, 54, 61, or 59.

SevenSegmentDisplayLabels.png

3-to-8 Decoder

  • An active high 3-to-8 decoder has the following truth table:
b2  b1  b0  |  y0  y1  y2  y3  y4  y5  y6  y7
------------|---------------------------------
 0   0   0  |   1   0   0   0   0   0   0   0
 0   0   1  |   0   1   0   0   0   0   0   0
 0   1   0  |   0   0   1   0   0   0   0   0
 0   1   1  |   0   0   0   1   0   0   0   0
 1   0   0  |   0   0   0   0   1   0   0   0
 1   0   1  |   0   0   0   0   0   1   0   0
 1   1   0  |   0   0   0   0   0   0   1   0
 1   1   1  |   0   0   0   0   0   0   0   1
 
  • From this truth table, we can see that each output signal is generated by ANDing the corresponding three input signals.

Schematics

  1. Open the ISE Design Suite and create a new project with Schematics as the Top-level source type.
  2. Add a new source of type Schematics to the project.
  3. Wire up the circuit for a 3-to-8 decoder according to the above truth table in the Schematic Capture Window. NOTE: remember that the CoolRunner-II is active low, so be sure to invert both the inputs and the outputs.
  4. We will be using on column of the Seven Segment Display to show our output signals. In addition to the circuit for the 3-to-8 decoder, find the ground symbol and place it in the Schematics Capture Window and connect it to an output marker titled E for enable. This is the enabler for one column of the Seven Segment Display.

ThreeToEightDecoderSchematic.png

  1. Add a new source of type Implementations Constraint File.
  2. Declare nets titled B2, B1, and B0 and assign them to sw1, sw0, and btn1 respectively.
  3. Declare nets titled Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and assign them to ca, cb, cc, cd, ce, cf, cg, and dp respectively.
  4. Finally declare a net titled E and assign it to one of the Seven Segment Display column pins.
NET B2     LOC = P124;
NET B1     LOC = P39;
NET B0     LOC = P94;

NET Y0     LOC = P56;
NET Y1     LOC = P53;
NET Y2     LOC = P60;
NET Y3     LOC = P58;
NET Y4     LOC = P57;
NET Y5     LOC = P54;
NET Y6     LOC = P61;
NET Y7     LOC = P59;
NET E      LOC = P126;
  1. Generate the programming file. Debug any errors that may occur. Once the program generation process comes to a completion, connect the CoolRunner-II to the computer and open up the CoolRunner-II Utility Window.
  2. Press the Erase button to remove any existing program from the CPLD.
  3. Press the "..." button. Browse to the project folder and double-click on the .jed file in that folder.
  4. Press the Program button. Once the CPLD has been programmed, play with it to see if its behavior matches that described by the truth table for the 3-to-8 decoder (the LEDs should light up in the order a, b, c, d, e, f, g, dp).

ThreeToEightDecoderPic.jpg

Verilog

  1. Open the ISE Design Suite and create a new project with HDL as the Top-level source type.
  2. Add a new source of type Verilog Module to the project. Define inputs B2, B1, and B0 and outputs Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, and E.
  3. The following is the code used for the 3-to-8 decoder:
//Reference time unit set to 1 nanosecond and precision is 1 picosecond
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College 
// Engineer:		Tiffany Q. Liu
// 
// Create Date:		02:31:52 11/14/2011 
// Module Name:         ThreeToEightDecoder.v 
// Project Name:	ThreeToEightDecoder-Verilog 
// Target Devices:	CoolRunner-II 
// Description:		Uses the Seven Segment Display to show output signals to a 
//                      3-to-8 decoder.
//////////////////////////////////////////////////////////////////////////////////
module ThreeToEightDecoder(
    input B2,
    input B1,
    input B0,
    output Y0,
    output Y1,
    output Y2,
    output Y3,
    output Y4,
    output Y5,
    output Y6,
    output Y7,
    output E
    );

	//Internal wire declarations
	wire iB2, iB1, iB0;
	wire iY0, iY1, iY2, iY3, iY4, iY5, iY6, iY7;
	 
	//Create inverse B2, B1, and B0 signals
	not (iB2, B2);
	not (iB1, B1);
	not (iB0, B0);
	
	//Create inverse output signals
	and (iY0, B2, B1, B0);
	and (iY1, B2, B1, iB0);
	and (iY2, B2, iB1, B0);
	and (iY3, B2, iB1, iB0);
	and (iY4, iB2, B1, B0);
	and (iY5, iB2, B1, iB0);
	and (iY6, iB2, iB1, B0);
	and (iY7, iB2, iB1, iB0);
	
	//Create output signals
	not (Y0, iY0);
	not (Y1, iY1);
	not (Y2, iY2);
	not (Y3, iY3);
	not (Y4, iY4);
	not (Y5, iY5);
	not (Y6, iY6);
	not (Y7, iY7);
	
	not (E, 1);

endmodule
 
  1. Add a new source of type Implementations Constraint File.
  2. Declare nets titled B2, B1, and B0 and assign them to sw1, sw0, and btn1 respectively.
  3. Declare nets titled Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and assign them to ca, cb, cc, cd, ce, cf, cg, and dp respectively.
  4. Finally declare a net titled E and assign it to one of the Seven Segment Display column pins.
NET B2     LOC = P124;
NET B1     LOC = P39;
NET B0     LOC = P94;

NET Y0     LOC = P56;
NET Y1     LOC = P53;
NET Y2     LOC = P60;
NET Y3     LOC = P58;
NET Y4     LOC = P57;
NET Y5     LOC = P54;
NET Y6     LOC = P61;
NET Y7     LOC = P59;
NET E      LOC = P126;
  1. Generate the programming file. Debug any errors that may occur. Once the program generation process comes to a completion, connect the CoolRunner-II to the computer and open up the CoolRunner-II Utility Window.
  2. Press the Erase button to remove any existing program from the CPLD.
  3. Press the "..." button. Browse to the project folder and double-click on the .jed file in that folder.
  4. Press the Program button. Once the CPLD has been programmed, play with it to see if its behavior matches that described by the truth table for the 3-to-8 decoder (the LEDs should light up in the order a, b, c, d, e, f, g, dp).

ThreeToEightDecoderPic.jpg

ISE Simulation

  1. Re-open the Verilog file for the 3-to-8 decoder if it was closed.
  2. Before coding the simulator module, we need to edit the Verilog module for the 3-to-8 decoder to remove the inverter gates from the inputs and outputs:
//Reference time unit set to 1 nanosecond and precision is 1 picosecond
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College 
// Engineer:		Tiffany Q. Liu
// 
// Create Date:		02:31:52 11/14/2011 
// Module Name:         ThreeToEightDecoder.v 
// Project Name:	ThreeToEightDecoder-Verilog 
// Target Devices:	CoolRunner-II 
// Description:		Uses the Seven Segment Display to show output signals to a 
//                      3-to-8 decoder.
//////////////////////////////////////////////////////////////////////////////////
module ThreeToEightDecoder(
    input B2,
    input B1,
    input B0,
    output Y0,
    output Y1,
    output Y2,
    output Y3,
    output Y4,
    output Y5,
    output Y6,
    output Y7,
    output E
    );
	 
	wire iB2, iB1, iB0;
	 
	//Create inverse B2, B1, and B0 signals
	not (iB2, B2);
	not (iB1, B1);
	not (iB0, B0);
	
	//Create output signals
	and (Y0, iB2, iB1, iB0);
	and (Y1, iB2, iB1, B0);
	and (Y2, iB2, B1, iB0);
	and (Y3, iB2, B1, B0);
	and (Y4, B2, iB1, iB0);
	and (Y5, B2, iB1, B0);
	and (Y6, B2, B1, iB0);
	and (Y7, B2, B1, B0);

	not(E, 1);

endmodule
 
  1. After editing the Verilog Module, add a new source of type Verilog Test Fixture to the project.
  2. Open the Verilog test fixture in the HDL editor. The following is the code we will use to test our Verilog 3-to-8 decoder file:
//Reference time unit set to 1 nanosecond and precision is 1 picosecond
`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College 
// Engineer:		Tiffany Q. Liu
//
// Create Date:         16:16:34 11/14/2011
// Design Name:         ThreeToEightDecoder
// Module Name:         ThreeToEightDecoder_Test.v
// Project Name:        ThreeToEightDecoder-Verilog
// Target Device:       CoolRunner-II
// Description:         Verilog Test Fixture created by ISE for module: ThreeToEightDecoder
////////////////////////////////////////////////////////////////////////////////

module ThreeToEightDecoder_Test;

	// Inputs
	reg B2;
	reg B1;
	reg B0;

	// Outputs
	wire Y0;
	wire Y1;
	wire Y2;
	wire Y3;
	wire Y4;
	wire Y5;
	wire Y6;
	wire Y7;
	wire E;

	// Instantiate the Unit Under Test (UUT)
	ThreeToEightDecoder uut (
		.B2(B2), 
		.B1(B1), 
		.B0(B0), 
		.Y0(Y0), 
		.Y1(Y1), 
		.Y2(Y2), 
		.Y3(Y3), 
		.Y4(Y4), 
		.Y5(Y5), 
		.Y6(Y6), 
		.Y7(Y7), 
		.E(E)
	);

	initial begin
		// Initialize Inputs
		B2 = 0;
		B1 = 0;
		B0 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		#10 B0 = 1;
		
		#10 B1 = 1;
		    B0 = 0;
		
		#10 B0 = 1;
		
		#10 B2 = 1;
		    B1 = 0;
		    B0 = 0;
		
		#10 B0 = 1;
		
		#10 B1 = 1;
		    B0 = 0;
		
		#10 B0 = 1;

	end
      
endmodule
 
  1. Save the test fixture and select it in the sources window by clicking on it once.
  2. Go to the Processes window, expand the ISim Simulator and double-click Behavioral Check Syntax. If any errors occur, debug the code.
  3. Once behavioral syntax check has passed, double-click on Simulate Behavioral Model.
  4. Use the Zoom to Full View tool, located to the right of the magnifying glasses on the simulation panel toolbar, to see the full view of the simulation.
  5. Now use the magnifying glass with the plus sign to zoom in until all relevant signals are captured in full size in the screen.
  6. Check the signals and see if they match the expected characteristics of a 3-to-8 decoder.

ThreeToEightDecoderSignal.png


CSC270 Lab 6

  • Author: Tiffany Liu
  • Date Created: November 23, 2011

Frequency Divider

For the following to state machines, we need to bring the clock frequency down to ~1Hz to observe the behavior of the outputs on the 
LED display. Unfortunately, the slowest clock frequency on the CoolRunner-II is 10kHz. Thus we need a frequency divider circuit. 
  • For this lab we will set the CoolRunner-II's clock to a frequency of 1MHz by placing the jumper over the bottom two pins:

CoolRunnerIIClockJumpers.png

  • When working in Schematics, we are limited by the "hardware", so we will use five divide by 16 circuits in sequence to bring the frequency down to ~0.95Hz.
  • When working in Verilog, we can be more precise with our divider and define it to be a divide by 1,000,000. This way we will be able to bring the frequency down closer to 1Hz.

Finite State Machine 1

  • Build a state-machine with 2 flip-flops with the following connections:

FiniteStateMachine1Circuit.png

  • This state-machine should have the following state diagram:

FiniteStateMachine1StateDiagram.png

Schematics

  1. Download the following file and unzip to use for the frequency divider: Frequency Divider Schematics Zip
  2. Open the ISE Design Suite and create a new project with Schematics as the Top-level source type.
  3. Add the schematic sources that were downloaded from Step 1 to the project.
    1. Go to Project --> Add source... Navigate to the folder that you saved the files downloaded from Step 1 and double-click on the schematic source file titled divide2Power20.
    2. Add a second source to the project following the same directions as above, double-clicking on the schematic source file titled divide16.
  4. Highlight the divide2Power20 schematics file in the Sources window. Expand Design Utilities in the Processes window and double-click on Create Schematics Symbol.
  5. Add a new source file of type schematic to the project for FSM 1.
  6. In the Sources window, right-click on the schematic source file for FSM 1 and select Set as Top Module. If a window pops up, choose OK.
  7. Wire up State-Machine 1 according the circuit diagram shown above. Use fdcp for the two flip-flops. Connect the output clkout of the divide2Power20 module to the clocks of the flip-flops (C). NOTE: remember that the CoolRunner-II is active low, so be sure to invert both the inputs and the outputs for I/O pins. Once finished, your schematic should look something like the following:

Fsm1 schematic.png

  1. Add a new source of type Implementations Constraint File.
  2. Declare nets titled preset, clear, and clk and assign them to sw0, sw1, and Pin 38 respectively.
  3. Declare nets titled Q1 and Q0 and assign them to LED0 and LED1 respectively.
NET preset     LOC = P39;
NET clear      LOC = P124;
NET clk        LOC = P38;

NET Q1         LOC = P68;
NET Q0         LOC = P69;
  1. Generate the programming file. Debug any errors that may occur. Once the program generation comes to completion, connect the CoolRunner-II to the computer and open up the CoolRunner-II Utility Window.
  2. Press the Erase button to remove any existing program from the CPLD.
  3. Press the "..." button. Browse to the project folder and double-click on the .jed file in that folder.
  4. Press the Program button.
  5. By default, the switches should be in the off position (slide left). Observe the LEDs. Q1 and Q0 should have three states: 1 and 0, 0 and 1, and 0 and 0 for LED1 and LED0 respectively. Activate sw0 (slide right). The FSM should now exist in a fourth state where LED1 and LED0 are 1 and 1. Deactivate sw0 (slide left) and the LEDs should go back to exhibiting the three states seen previous to the switch activation.

Verilog

  1. Download the following file and unzip to use for the frequency divider: Frequency Divider Verilog Zip
  2. Open the ISE Design Suite and create a new project with HDL as the Top-level source type.
  3. Add the Verilog module source that was downloaded from Step 1 to the project.
    • Go to Project --> Add source... Navigate to the folder that you saved the files downloaded from Step 1 and double-click on the Verilog module source file titled divide1M.v
  4. Add a new source file of type Verilog module to the project for FSM 1. Define inputs clear, preset, and clock and outputs Q1 and Q0.
  5. In the Sources window, right-click on the Verilog module source file for FSM 1 and select Set as Top Module. If a window pops up, choose OK.
  6. The following is the code used for FSM1 NOTE: remember that the CoolRunner-II is active low, so be sure to invert both the inputs and the outputs for I/O pins:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College 
// Engineer:		Tiffany Q. Liu
// 
// Create Date:    	14:20:10 11/24/2011  
// Module Name:    	FSM1 
// Project Name:	FiniteStateMachine1-Verilog 
// Target Devices:	CoolRunner-II
// Description:		Verilog version of FSM 1 from CSC270 Lab 6
//
// Dependencies:	divide1M.v - used as frequency divider
//////////////////////////////////////////////////////////////////////////////////
module FSM1(
	input clear,
	input preset,
	input clock,
	output Q1,
	output Q0
    );

	wire outputClk;			//frequency-divided clock signal ~1Hz
	wire invClear, invPreset;       //inverse clear and preset signals
	wire d1;			//data signal for second flip-flop
	wire invQ1, invQ0;		//inverse Q1 and Q0 signals
	
	//Divide the frequency of clock to slow down to ~1Hz:
	divide1M clockDivider (.clkin(clock), .reset(0), .clkout(outputClk));
	
	//Define inverse clear and preset signals for active-low CR-II switches:
	not (invClear, clear);
	not (invPreset, preset);
	
	//Define FSM1 with two D flip-flops and a nor gate:
	FDCP ff0 (.C(outputClk), .CLR(invClear), .D(invQ0), .PRE(invPreset), .Q(invQ1));
	nor (d1, invQ1, invQ0);
	FDCP ff1 (.C(outputClk), .CLR(invClear), .D(d1), .PRE(invPreset), .Q(invQ0));
	
	//Define inverse Q1 and Q0 signals for active-low CR-II LEDs:
	not(Q1, invQ1);
	not(Q0, invQ0);

endmodule
 
  1. Add a new source of type Implementations Constraint File.
  2. Declare nets titled preset, clear, and clock and assign them to sw0, sw1, and Pin 38 respectively.
  3. Declare nets titled Q1 and Q0 and assign them to LED0 and LED1 respectively.
NET preset     LOC = P39;
NET clear      LOC = P124;
NET clock      LOC = P38;

NET Q1         LOC = P68;
NET Q0         LOC = P69;
  1. Generate the programming file. Debug any errors that may occur. Once the program generation comes to completion, connect the CoolRunner-II to the computer and open up the CoolRunner-II Utility Window.
  2. Press the Erase button to remove any existing program from the CPLD.
  3. Press the "..." button. Browse to the project folder and double-click on the .jed file in that folder.
  4. Press the Program button.
  5. By default, the switches should be in the off position (slide left). Observe the LEDs. Q1 and Q0 should have three states: 1 and 0, 0 and 1, and 0 and 0 for LED1 and LED0 respectively. Activate sw0 (slide right). The FSM should now exist in a fourth state where LED1 and LED0 are 1 and 1. Deactivate sw0 (slide left) and the LEDs should go back to exhibiting the three states seen previous to the switch activation.

ISE Simulator

  1. Re-open the Verilog file for Finite State Machine 1 if it was closed.
  2. Before coding the simulator module, we need to edit the Verilog module for FSM1 to remove the inverter gates from the inputs and outputs:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College 
// Engineer:		Tiffany Q. Liu
// 
// Create Date:    	14:20:10 11/24/2011  
// Module Name:    	FSM1 
// Project Name:	FiniteStateMachine1-Verilog 
// Target Devices:	CoolRunner-II
// Description:		Verilog version of FSM 1 from CSC270 Lab 6
//
// Dependencies:	divide1M.v - used as frequency divider
//////////////////////////////////////////////////////////////////////////////////
module FSM1(
	input clear,
	input preset,
	input clock,
	output Q1,
	output Q0
    );
	
	wire d1;		//data signal for second flip-flop
	
	//Define FSM1 with two D flip-flops and a nor gate:
	FDCP ff0 (.C(clock), .CLR(clear), .D(Q0), .PRE(preset), .Q(Q1));
	nor (d1, Q1, Q0);
	FDCP ff1 (.C(clock), .CLR(clear), .D(d1), .PRE(preset), .Q(Q0));

endmodule
 
  1. After editing the Verilog Module, add a new source of type Verilog Test Fixture to the project.
  2. Open the Verilog test fixture in the HDL editor. The following is the code we will use to test our Verilog FSM 1 file:
`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College 
// Engineer:		Tiffany Q. Liu
//
// Create Date:         16:24:17 11/24/2011
// Module Name:	        FSM1_Test.v
// Project Name:	FiniteStateMachine1-Verilog
// Target Device:	CoolRunner-II 
// Description:	        Verilog Test Fixture created by ISE for module: FSM1
////////////////////////////////////////////////////////////////////////////////

module FSM1_Test;

	// Inputs
	reg clear;
	reg preset;
	reg clock;

	// Outputs
	wire Q1;
	wire Q0;
	
	integer count = 0;

	// Instantiate the Unit Under Test (UUT)
	FSM1 uut (
	   .clear(clear), 
	   .preset(preset), 
	   .clock(clock), 
	   .Q1(Q1), 
	   .Q0(Q0)
	);

	initial begin
	   // Initialize Inputs
	   clear = 0;
	   preset = 0;
	   clock = 0;
	end

        always begin  
	   // Add stimulus here
	   if (count >= 10) begin
	      preset = 1;
	      clock = 1;
	      #10;
	      clock = 0;
	      #10;
	   end
	   else begin
	      preset = 0;
	      clock = 1;
	      #10;
	      clock = 0;
	      #10;
	   end
	   count = count + 1;
	   if (count >= 20) begin
	      count = 0;
	   end
	end
      
endmodule
 
  1. Save the test fixture and select it in the sources window by clicking on it once.
  2. Go to the Processes window, expand the ISim Simulator and double-click Behavioral Check Syntax. If any errors occur, debug the code.
  3. Once behavioral syntax check has passed, double-click on Simulate Behavioral Model.
  4. Use the Zoom to Full View tool, located to the right of the magnifying glasses on the simulation panel toolbar, to see the full view of the simulation.
  5. Now use the magnifying glass with the plus sign to zoom in until all relevant signals are captured in full size in the screen.
  6. If necessary, press the play arrow, eleventh icon from the right of the magnifying glass with the plus sign, to generate more signals.
  7. Check the signals and see if they match the expected characteristics of the FSM 1.

FSM1Signal.png


Finite State Machine 2

  • Build a state-machine with 2 flip-flops with the following connections:

FiniteStateMachine2Circuit.png

  • This state-machine will have the following state diagram:

FiniteStateMachine2StateDiagram.png

Schematics

  1. Download the following files to use for the frequency divider: Frequency Divider Schematics Zip
  2. Open the ISE Design Suite and create a new project with Schematics as the Top-level source type.
  3. Add the schematic sources that were downloaded from Step 1 to the project.
    1. Go to Project --> Add source... Navigate to the folder that you saved the files downloaded from Step 1 and double-click on the schematic source file titled divide2Power20.
    2. Add a second source to the project following the same directions as above, double-clicking on the schematic source file titled divide16.
  4. Highlight the divide2Power20 schematics file in the Sources window. Expand Design Utilities in the Processes window and double-click on Create Schematics Symbol.
  5. Add a new source file of type schematic to the project for FSM 2.
  6. In the Sources window, right-click on the schematic source file for FSM 2 and select Set as Top Module. If a window pops up, choose OK.
  7. Wire up State-Machine 2 according the circuit diagram shown above. Use fdcp for the two flip-flops. Connect the output clkout of the divide2Power20 module to the clocks of the flip-flops (C). NOTE: remember that the CoolRunner-II is active low, so be sure to invert both the inputs and the outputs for I/O pins. Once finished, your schematic should look something like the following:

Fsm2 schematic.png

  1. Add a new source of type Implementations Constraint File.
  2. Declare nets titled preset, clear, and clk and assign them to sw0, sw1, and Pin 38 respectively.
  3. Declare nets titled Q1 and Q0 and assign them to LED0 and LED1 respectively.
NET preset     LOC = P39;
NET clear      LOC = P124;
NET clk        LOC = P38;

NET Q1         LOC = P68;
NET Q0         LOC = P69;
  1. Generate the programming file. Debug any errors that may occur. Once the program generation comes to completion, connect the CoolRunner-II to the computer and open up the CoolRunner-II Utility Window.
  2. Press the Erase button to remove any existing program from the CPLD.
  3. Press the "..." button. Browse to the project folder and double-click on the .jed file in that folder.
  4. Press the Program button.
  5. By default, the switches should be in the off position (slide left). Observe the LEDs. Q1 and Q0 should have three states: 1 and 0, 0 and 1, and 0 and 0 for LED1 and LED0 respectively. Activate sw0 (slide right). The FSM should now exist in a fourth state where LED1 and LED0 are 1 and 1. Deactivate sw0 (slide left) and the LEDs could either remain stuck in the fourth state. To get the LEDs back to exhibiting the three states that were seen prior to activating sw0, activate sw1 (slide right) while sw0 remains deactivated (slide left) and then deactivate sw1 (slide left).

Verilog

  1. Download the following file and unzip to use for the frequency divider: Frequency Divider Verilog Zip
  2. Open the ISE Design Suite and create a new project with HDL as the Top-level source type.
  3. Add the Verilog module source that was downloaded from Step 1 to the project.
    • Go to Project --> Add source... Navigate to the folder that you saved the files downloaded from Step 1 and double-click on the Verilog module source file titled divide1M.v
  4. Add a new source file of type Verilog module to the project for FSM 2. Define inputs clear, preset, and clock and outputs Q1 and Q0.
  5. In the Sources window, right-click on the Verilog module source file for FSM 2 and select Set as Top Module. If a window pops up, choose OK.
  6. The following is the code used for FSM2 NOTE: remember that the CoolRunner-II is active low, so be sure to invert both the inputs and the outputs for I/O pins:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College
// Engineer:		Tiffany Q. Liu
// 
// Create Date:    	19:32:31 11/24/2011 
// Module Name:	FSM2 
// Project Name:	FiniteStateMachine2-Verilog
// Target Devices:	CoolRunner-II
// Description:		Verilog version of FSM 2 from CSC270 Lab 6
//
// Dependencies:	divide1M.v - used as a frequency divider
//////////////////////////////////////////////////////////////////////////////////
module FSM2(
	input clear,
	input preset,
	input clock,
	output Q1,
	output Q0
    );

	wire outputClk;			//frequency-divided clock signal ~1Hz
	wire invClear, invPreset;	//inverse clear and preset signals
	wire invD1;			//inverse data signal for second flip-flop
	wire d1;			//data signal for second flip-flop
	wire invQ1, invQ0;		//inverse Q1 and Q0 signals
	
	//Divide the frequency of clock to slow down to ~1Hz:
	divide1M clockDivider (.clkin(clock), .reset(0), .clkout(outputClk));
	
	//Define inverse clear and preset signals for active-low CR-II switches:
	not (invClear, clear);
	not (invPreset, preset);
	
	//Define FSM1 with two D flip-flops and a nor gate:
	FDCP ff0 (.C(outputClk), .CLR(invClear), .D(invQ0), .PRE(invPreset), .Q(invQ1));
	xor (invD1, invQ1, invQ0);
	not (d1, invD1);
	FDCP ff1 (.C(outputClk), .CLR(invClear), .D(d1), .PRE(invPreset), .Q(invQ0));
	
	//Define inverse Q1 and Q0 signals for active-low CR-II LEDs:
	not(Q1, invQ1);
	not(Q0, invQ0);

endmodule
 
  1. Add a new source of type Implementations Constraint File.
  2. Declare nets titled preset, clear, and clock and assign them to sw0, sw1, and Pin 38 respectively.
  3. Declare nets titled Q1 and Q0 and assign them to LED0 and LED1 respectively.
NET preset     LOC = P39;
NET clear      LOC = P124;
NET clock      LOC = P38;

NET Q1         LOC = P68;
NET Q0         LOC = P69;
  1. Generate the programming file. Debug any errors that may occur. Once the program generation comes to completion, connect the CoolRunner-II to the computer and open up the CoolRunner-II Utility Window.
  2. Press the Erase button to remove any existing program from the CPLD.
  3. Press the "..." button. Browse to the project folder and double-click on the .jed file in that folder.
  4. Press the Program button.
  5. By default, the switches should be in the off position (slide left). Observe the LEDs. Q1 and Q0 should have three states: 1 and 0, 0 and 1, and 0 and 0 for LED1 and LED0 respectively. Activate sw0 (slide right). The FSM should now exist in a fourth state where LED1 and LED0 are 1 and 1. Deactivate sw0 (slide left) and the LEDs could either remain stuck in the fourth state. To get the LEDs back to exhibiting the three states that were seen prior to activating sw0, activate sw1 (slide right) while sw0 remains deactivated (slide left) and then deactivate sw1 (slide left).

ISE Simulator

  1. Re-open the Verilog file for Finite State Machine 2 if it was closed.
  2. Before coding the simulator module, we need to edit the Verilog module for FSM2 to remove the inverter gates from the inputs and outputs:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College
// Engineer:		Tiffany Q. Liu
// 
// Create Date:    	19:32:31 11/24/2011 
// Module Name:	        FSM2 
// Project Name:	FiniteStateMachine2-Verilog
// Target Devices:	CoolRunner-II
// Description:		Verilog version of FSM 2 from CSC270 Lab 6
//
// Dependencies:	divide1M.v - used as a frequency divider
//////////////////////////////////////////////////////////////////////////////////
module FSM2(
	input clear,
	input preset,
	input clock,
	output Q1,
	output Q0
    );
	
	wire invD1;	        //inverse data signal for second flip-flop
	wire d1;		//data signal for second flip-flop
	
	//Define FSM1 with two D flip-flops and a nor gate:
	FDCP ff0 (.C(clock), .CLR(clear), .D(Q0), .PRE(preset), .Q(Q1));
	xor (invD1, Q1, Q0);
	not (d1, invD1);
	FDCP ff1 (.C(clock), .CLR(clear), .D(d1), .PRE(preset), .Q(Q0));


endmodule
 
  1. After editing the Verilog Module, add a new source of type Verilog Test Fixture to the project.
  2. Open the Verilog test fixture in the HDL editor. The following is the code we will use to test our Verilog FSM 2 file:
`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College 
// Engineer:		Tiffany Q. Liu
//
// Create Date:         02:32:11 11/25/2011
// Module Name:	        FSM2_test.v
// Project Name:        FiniteStateMachine2-Verilog
// Target Device:	CoolRunner-II 
// Description:	        Verilog Test Fixture created by ISE for module: FSM2
////////////////////////////////////////////////////////////////////////////////

module FSM2_test;

	// Inputs
	reg clear;
	reg preset;
	reg clock;

	// Outputs
	wire Q1;
	wire Q0;
	
	integer count = 0;

	// Instantiate the Unit Under Test (UUT)
	FSM2 uut (
	   .clear(clear), 
	   .preset(preset), 
	   .clock(clock), 
	   .Q1(Q1), 
	   .Q0(Q0)
	);

	initial begin
	   // Initialize Inputs
	   clear = 0;
	   preset = 0;
	   clock = 0;
	end

        always begin  
	   // Add stimulus here
	   if (count >= 20) begin
	      preset = 1;
	      clock = 1;
	      #10;
	      clock = 0;
	      #10;
	   end
	   else begin
	      preset = 0;
	      clock = 1;
	      #10;
              clock = 0;
	      #10;
	   end
	   count = count + 1;
	   if (count >= 40) begin
	      count = 0;
	   end
	end
      
endmodule
 
  1. Save the test fixture and select it in the sources window by clicking on it once.
  2. Go to the Processes window, expand the ISim Simulator and double-click Behavioral Check Syntax. If any errors occur, debug the code.
  3. Once behavioral syntax check has passed, double-click on Simulate Behavioral Model.
  4. Use the Zoom to Full View tool, located to the right of the magnifying glasses on the simulation panel toolbar, to see the full view of the simulation.
  5. Now use the magnifying glass with the plus sign to zoom in until all relevant signals are captured in full size in the screen.
  6. If necessary, press the play arrow, eleventh icon from the right of the magnifying glass with the plus sign, to generate more signals.
  7. Check the signals and see if they match the expected characteristics of the FSM 2.

FSM2Signal.png


CSC270 Lab 7

  • Author: Tiffany Liu
  • Date Created: November 24, 2011

Frequency Divider

For the following to state machines, we need to bring the clock frequency down to ~1Hz to observe the behavior of the outputs on the 
LED display. Unfortunately, the slowest clock frequency on the CoolRunner-II is 10kHz. Thus we need a frequency divider circuit. 
  • For this lab we will set the CoolRunner-II's clock to a frequency of 1MHz by placing the jumper over the bottom two pins:

CoolRunnerIIClockJumpers.png

  • When working in Schematics, we are limited by the "hardware", so we will use five divide by 16 circuits in sequence to bring the frequency down to ~0.95Hz.
  • When working in Verilog, we can be more precise with our divider and define it to be a divide by 1,000,000. This way we will be able to bring the frequency down closer to 1Hz.

GYR Sequencer

The focus of this lab is to build a 4-state sequencer that activates 3 output LEDs that represent the Green, Yellow, 
and Red traffic lights.
  • The traffic light sequencer functions according to the following state diagram:

GYRSequencerStateDiagram.png

  • When working in Schematics, we will wire up the GYR sequencer the same way done in CSC270 Lab 7.
  • When working in Verilog, we can actually define our module in the manner of a state machine with case constructs.


Schematics

  1. Download the following files to use for the frequency divider: Frequency Divider Schematics Zip
  2. Open the ISE Design Suite and create a new project with Schematics as the Top-level source type.
  3. Add the schematic sources that were downloaded from Step 1 to the project.
    1. Go to Project --> Add source... Navigate to the folder that you saved the files downloaded from Step 1 and double-click on the schematic source file titled divide2Power20.
    2. Add a second source to the project following the same directions as above, double-clicking on the schematic source file titled divide16.
  4. Highlight the divide2Power20 schematics file in the Sources window. Expand Design Utilities in the Processes window and double-click on Create Schematics Symbol.
  5. Add a new source file of type schematic to the project for GYR Sequencer.
  6. In the Sources window, right-click on the schematic source file for GYR Sequencer and select Set as Top Module. If a window pops up, choose OK.
  7. Wire up traffic sequencer according to the following circuit diagram shown below. Use fdcp for the two flip-flops. Connect the output clkout of the divide2Power20 module to the clocks of the flip-flops (C). NOTE: remember that the CoolRunner-II is active low, so be sure to invert both the inputs and the outputs for I/O pins.

GyrSequencer circuit.png

  1. Once finished, your schematic should look something like the following:

GyrSequencer schematic.png

  1. Add a new source of type Implementations Constraint File.
  2. Declare nets titled preset, clear, and clk and assign them to sw0, sw1, and Pin 38 respectively.
  3. Declare nets titled G, Y, and R and assign them to LED0, LED1, and LED2 respectively.
NET preset     LOC = P39;
NET clear      LOC = P124;
NET clk        LOC = P38;

NET G          LOC = P69;
NET Y          LOC = P68;
NET R          LOC = P66;
  1. Generate the programming file. Debug any errors that may occur. Once the program generation comes to completion, connect the CoolRunner-II to the computer and open up the CoolRunner-II Utility Window.
  2. Press the Erase button to remove any existing program from the CPLD.
  3. Press the "..." button. Browse to the project folder and double-click on the .jed file in that folder.
  4. Press the Program button.
  5. By default, the switches should be in the off position (slide left). Observe the LEDs. G, Y, and R should have three states: 0, 0, and 1, followed by 1, 0, and 0, and finally 0, 1, and 0 for LED0, LED1, and LED2 respectively. Activate sw0 (slide right). The traffic light sequencer should now exist in a fourth state where LED0, LED1, and LED2 are 0, 0, and 1 respectively. Deactivate sw0 (slide left) and the LEDs should remain in that state. Then activate sw1 (slide right) to reset the system and deactivate sw1 (slide left) and the traffic light sequencer should exhibit the three states that were seen prior to activating and deactivating sw0.

Verilog

  1. Download the following file and unzip to use for the frequency divider: Frequency Divider Verilog Zip
  2. Open the ISE Design Suite and create a new project with HDL as the Top-level source type.
  3. Add the Verilog module source that was downloaded from Step 1 to the project.
    • Go to Project --> Add source... Navigate to the folder that you saved the files downloaded from Step 1 and double-click on the Verilog module source file titled divide1M.v
  4. Add a new source file of type Verilog module to the project for GYR Sequencer. Define inputs reset, preset, and clock and outputs G, Y, and R.
  5. In the Sources window, right-click on the Verilog module source file for GYR Sequencer and select Set as Top Module. If a window pops up, choose OK.
  6. The following is the code used for GYR Sequencer NOTE: remember that the CoolRunner-II is active low, so be sure to invert both the inputs and the outputs for I/O pins:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College 
// Engineer:		Tiffany Q. Liu
// 
// Create Date:		22:43:22 11/24/2011 
// Module Name:	        GYRSequencer 
// Project Name:	TrafficLightSequencer-Verilog
// Target Devices:	CoolRunner-II
// Description:		Verilog version of GYR sequencer from CSC270 Lab 7
//
// Dependencies:	divide1M.v - used for clock frequency divider
//////////////////////////////////////////////////////////////////////////////////
module GYRSequencer(clock, reset, preset, G, Y, R);

   input clock, reset, preset;
   output G, Y, R;
   reg G, Y, R;

   parameter S0 = 2'b00;	//State 0
   parameter S1 = 2'b01;	//State 1
   parameter S2 = 2'b10;	//State 2
   parameter S3 = 2'b11;	//State 3

   (* FSM_ENCODING="SEQUENTIAL", SAFE_IMPLEMENTATION="NO" *) 
   reg [1:0] state = S0;	//Initialize to State 0
	
   //Divide master clock frequency to bring clock down to ~1Hz
   wire outputClk;
   divide1M clkDivider (.clkin(clock), .clkout(outputClk));

   always@(posedge outputClk)
      //When reset is activated (active low), go back to State 0
      if (!reset) begin
         state <= S0;
         G = 1;
	 Y = 1;
	 R = 0;
      end
      //When preset is activated (active low), go to State 3
      else if (!preset) begin
	 state <= S3;
	 G = 1;
	 Y = 1;
	 R = 0;
      end
      else
         (* FULL_CASE, PARALLEL_CASE *)
	 //State 0 (G'Y'R - active low) --> State 1 (GY'R' - active low)
	 //State 1 (GY'R' - active low) --> State 2 (G'YR' - active low)
	 //State 2 (G'YR' - active low) --> State 0 (G'Y'R - active low)
	 //State 3 (G'Y'R - active low) --> State 3 (G'Y'R - active low)
	 case (state)
            S0 : begin
               state <= S1;
               G = 1;
	       Y = 1;
	       R = 0;
            end
            S1 : begin
	       state <= S2;
               G = 0;
	       Y = 1;
	       R = 1;
            end
            S2 : begin
	       state <= S0;
	       G = 1;
	       Y = 0;
	       R = 1;
            end
            S3 : begin
               state <= S3;
               G = 1;
	       Y = 1;
	       R = 0;
            end
         endcase

endmodule
 
  1. Add a new source of type Implementations Constraint File.
  2. Declare nets titled preset, clear, and clock and assign them to sw0, sw1, and Pin 38 respectively.
  3. Declare nets titled G, Y, and R and assign them to LED0, LED1, and LED2 respectively.
NET preset     LOC = P39;
NET reset      LOC = P124;
NET clock      LOC = P38;

NET G          LOC = P69;
NET Y          LOC = P68;
NET R          LOC = P66;
  1. Generate the programming file. Debug any errors that may occur. Once the program generation comes to completion, connect the CoolRunner-II to the computer and open up the CoolRunner-II Utility Window.
  2. Press the Erase button to remove any existing program from the CPLD.
  3. Press the "..." button. Browse to the project folder and double-click on the .jed file in that folder.
  4. Press the Program button.
  5. By default, the switches should be in the off position (slide left). Observe the LEDs. G, Y, and R should have three states: 0, 0, and 1, followed by 1, 0, and 0, and finally 0, 1, and 0 for LED0, LED1, and LED2 respectively. Activate sw0 (slide right). The traffic light sequencer should now exist in a fourth state where LED0, LED1, and LED2 are 0, 0, and 1 respectively. Deactivate sw0 (slide left) and the LEDs should remain in that state. Then activate sw1 (slide right) to reset the system and deactivate sw1 (slide left) and the traffic light sequencer should exhibit the three states that were seen prior to activating and deactivating sw0.

ISE Simulator

  1. Re-open the Verilog file for Traffic Light Sequencer if it was closed.
  2. Before coding the simulator module, we need to edit the Verilog module for GYR Sequencer to remove the inverter gates from the inputs and outputs:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College 
// Engineer:		Tiffany Q. Liu
// 
// Create Date:		22:43:22 11/24/2011 
// Module Name:	        GYRSequencer 
// Project Name:	TrafficLightSequencer-Verilog
// Target Devices:	CoolRunner-II
// Description:		Verilog version of GYR sequencer from CSC270 Lab 7
//
// Dependencies:	divide1M.v - used for clock frequency divider
//////////////////////////////////////////////////////////////////////////////////
module GYRSequencer(clock, reset, preset, G, Y, R);

   input clock, reset, preset;
   output G, Y, R;
   reg G, Y, R;

   parameter S0 = 2'b00;	//State 0
   parameter S1 = 2'b01;	//State 1
   parameter S2 = 2'b10;	//State 2
   parameter S3 = 2'b11;	//State 3

   (* FSM_ENCODING="SEQUENTIAL", SAFE_IMPLEMENTATION="NO" *) 
   reg [1:0] state = S0;	//Initialize to State 0

   always@(posedge clock)
      //When reset is activated, go back to State 0
      if (reset) begin
         state <= S0;
         G = 0;
         Y = 0;
         R = 1;
      end
      //When preset is activated, go to State 3
      else if (preset) begin
         state <= S3;
         G = 0;
         Y = 0;
         R = 1;
      end
      else
         (* FULL_CASE, PARALLEL_CASE *)
         //State 0 (G'Y'R) --> State 1 (GY'R')
	 //State 1 (GY'R') --> State 2 (G'YR')
	 //State 2 (G'YR') --> State 0 (G'Y'R)
	 //State 3 (G'Y'R) --> State 3 (G'Y'R)
         case (state)
            S0 : begin
               state <= S1;
               G = 0;
               Y = 0;
	       R = 1;
            end
            S1 : begin
               state <= S2;
               G = 1;
	       Y = 0;
	       R = 0;
            end
            S2 : begin
               state <= S0;
	       G = 0;
	       Y = 1;
	       R = 0;
            end
            S3 : begin
	       state <= S3;
	       G = 0;
	       Y = 0;
	       R = 1;
            end
         endcase

endmodule
 
  1. After editing the Verilog Module, add a new source of type Verilog Test Fixture to the project.
  2. Open the Verilog test fixture in the HDL editor. The following is the code we will use to test our Verilog GYR Sequencer file:
`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:		Smith College 
// Engineer:		Tiffany Q. Liu
//
// Create Date:         03:20:26 11/25/2011
// Module Name:	        GYRSequencer_test.v
// Project Name:        TrafficLightSequencer-Verilog
// Target Device:	CoolRunner-II
// Description:	        Verilog Test Fixture created by ISE for module: GYRSequencer
////////////////////////////////////////////////////////////////////////////////

module GYRSequencer_test;

	// Inputs
	reg clock;
	reg reset;
	reg preset;

	// Outputs
	wire G;
	wire Y;
	wire R;
	
	integer count = 0;

	// Instantiate the Unit Under Test (UUT)
	GYRSequencer uut (
	   .clock(clock), 
	   .reset(reset), 
	   .preset(preset), 
	   .G(G), 
	   .Y(Y), 
	   .R(R)
	);

	initial begin
	   // Initialize Inputs
	   reset = 0;
	   preset = 0;
	   clock = 0;
	end

        always begin  
	   // Add stimulus here
	   if (count >= 20) begin
	      preset = 1;
	      clock = 1;
              #10;
	      clock = 0;
	      #10;
	   end
	   else begin
	      preset = 0;
	      clock = 1;
	      #10;
	      clock = 0;
	      #10;
	   end
	   count = count + 1;
	   if (count >= 40) begin
	      count = 0;
	   end
	end
      
endmodule
 
  1. Save the test fixture and select it in the sources window by clicking on it once.
  2. Go to the Processes window, expand the ISim Simulator and double-click Behavioral Check Syntax. If any errors occur, debug the code.
  3. Once behavioral syntax check has passed, double-click on Simulate Behavioral Model.
  4. Use the Zoom to Full View tool, located to the right of the magnifying glasses on the simulation panel toolbar, to see the full view of the simulation.
  5. Now use the magnifying glass with the plus sign to zoom in until all relevant signals are captured in full size in the screen.
  6. If necessary, press the play arrow, eleventh icon from the right of the magnifying glass with the plus sign, to generate more signals.
  7. Check the signals and see if they match the expected characteristics of the GYR Sequencer.

GYRSequencerSignal.png